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tb6551fg/fag 2012 - 09- 28 1 toshiba bi - cmos integrated circuit silicon monolithic tb65 51 fg, TB6551FAG 3 - p hase full - wave sine - wave pwm brushless motor control ler the tb65 51 fg/fag is designed for motor fan applications for t hree - phase brushless dc (bldc) motors. features ? sine - wave pwm control ? built - in triangular - wave generator ( carrier cycle = f osc /252 (hz)) ? built - in lead angle control function (0 to 58 in 32 steps) ? built - in dead time function (setti ng 2.6 s or 3.8 s) ? b ootstrap circuit compliant ? over - current protection signal input pin ? built - in regulator (v ref = 5 v (typ.), 30 ma (max)) ? oper ating supply voltage range: v cc = 6 v to 10 v tb6551fg TB6551FAG weight: ssop24 -p-300- 1.00 : 0.33 g (typ.) p - ssop24 - 0 613 - 1.00 - 001 : 0.28 g (typ.) p - ssop24 - 0613- 1.00 - 001
tb6551fg/fag 2012 - 09- 28 2 block diagram system clock generator position detector regulator counter 5 - bit ad 6 - bit triangular wave generator output waveform generator data select s witching 120 /180 and ga te block protection on/ off setting dead time charger 120 - turn - on matrix power - on reset protection & reset phase matching 4 bit s fg rotati ng direction st / sp cw / ccw err gb comparator comparator comparator comparator pwm hu hv hw 120 /180 phase w phase u phase v x in x ou t hu hv hw v e v cc p - gnd s - gnd v ref out res i dc cw / ccw fg rev 14 15 21 20 19 22 1 3 13 24 11 3 18 17 16 23 la 12 4 7 5 8 6 9 10 t d u x v y w z os internal reference voltage
tb6551fg/fag 2012 - 09- 28 3 pin description pin no. symbol description remarks 21 hu positional signal input pin u when positional signal is hhh or lll, gate block protection operates. with built - in pull - up resi stor 20 hv positional signal input pin v 19 hw positional signal input pin w 18 cw/ccw rotation direction signal input pin l: forward h: reverse 11 res reset - signal - input pin l: reset (output is non - active) operation/halt operation also used for g ate block protection 22 v e inputs voltage instruction signal with built - in pull - down resistor 23 la lead angle setting signal input pin sets 0 to 58 in 32 steps 12 os inputs output logic select signal l: active low h: active high 3 i dc inputs over - c urrent - protection - signal inputs dc link current. reference voltage: 0.5 v with built - in filter ( 1 s) 14 x in inputs clock signal with built - in feedback resistor 15 x out outputs clock signal 24 v refout outputs reference voltage signal 5 v (typ.), 30 ma (max) 17 fg fg signal output pin outputs 3ppr of positional signal 16 rev reverse rotation detection signal detects reverse rotation. 9 u outputs turn - on signal select active high or active low using the output logic select pin. 8 v outputs turn - on signal 7 w outputs turn - on signal 6 x outputs turn - on signal 5 y outputs turn - on signal 4 z outputs turn - on signal 1 v cc power supply voltage pin v cc = 6 v to 10 v 10 t d inputs setting dead time l: 3.8 s, h or open: 2.6 s 2 p - gnd ground for power supply ground pin 13 s - gnd ground for signals ground pin
tb6551fg/fag 2012 - 09- 28 4 input/output equivalent circuits pin description symbol input/output signal input/output internal circuit positional signal input pin u positional signal input pin v positional signal input pin w hu hv hw digital with schmitt trigger hysteresis 300 mv (typ.) l : 0.8 v (max) h: v refout ? 1 v (min) forward/reverse switching input pin l: forward (cw) h: reverse (ccw) cw/ccw digital with schm itt trigger hysteresis 300 mv (typ.) l : 0.8 v (max) h: v refout ? 1 v (min) reset input l: stops operation (reset). h: operates. res digital with schmitt trigger hysteresis 300 mv (typ.) l : 0.8 v (max) h: v refout ? 1 v (min) voltage instructio n signal input pin turn on the lower transistor at 0.2 v or less. (x, y, z pins: on duty of 8%) v e analog input range 0 v to 5.0 v input voltage of vrefout or higher is clipped to vrefout. lead angle setting signal input pin 0 v: 0 5 v: 58 (5 - bit ad) la analog input range 0 v to 5.0 v input voltage of v refout or higher is clipped to v refout . v ref out v ref out 240 k 2.4 k v ref out v refout 120 k 2.4 k v refout 120 k 2.4 k v cc 240 k 120 v cc 240 k 120
tb6551fg/fag 2012 - 09- 28 5 pin description symbol input/output signal input/output internal circuit setting dead time input pin l : 3.8 s h or open: 2.6 s t d digital l : 0.8 v (max) h: v refout ? 1 v (min) output logic select signal input pin l: active low h: active high os digital l : 0.8 v (max) h: v refout ? 1 v (min) over - current protection signal input pin i dc analog gate block protected at 0.5 v or higher (released at carrier cycle) clock signal input pin x in operating range 2 mhz to 8 mhz ( ceramic oscillation) clock signal output pin x out reference voltage signal output pin vrefout 5 0.5 v (max 30 ma) v ref out v refout 120 k 2.4 k v cc 0.5 v 240 k 5 pf comparator 360 k v refout v refout x out x in v ref out v refout 120 k 1.2 k v cc v cc v cc
tb6551fg/fag 2012 - 09- 28 6 pin description symbol input/output signal input/output internal circuit re verse - rotation - detection signal output pin rev digital push - pull output: 1 ma (max) fg signal output pin fg digital push - pull output: 1 ma (max) turn - on signal output pin u turn - on signal output pin v turn - on signal output pin w turn - on signa l output pin x turn - on signal output pin y turn - on signal output pin z u v w x y z analog push - pull output: 2 ma (max) l : 0.78 v (max) h: v refout ? 0.78 v (min) v refout v refout 120 v refout 120 v refout v refout 120
tb6551fg/fag 2012 - 09- 28 7 absolute maximum ratings (t a = 25c) characteristics symbol rating unit supply volta ge v cc 12 v input voltage v in (1) ? 0.3 to v cc (note 1) v v in (2) ? 0.3 to 5.5 (note 2) turn - on signal output current i out 2 ma power dissipation p d fg 0.9 (note 3) w fag 1.0 (note 3) operating temperature t opr ? 30 to 115 (note 4) c storage t emperature t stg ? 50 to 150 c note 1: v in (1) pin: v e , la note 2: v in (2) pin: hu, hv, hw, cw/ccw, res, os, i dc, t d note 3: when mounted on a pcb (universal 50 mm 50 mm 1.6 mm, cu 30%) note 4: operating temperature range is determined by the p d ? t a c haracteristic. note 5 : using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum ratings. please design the appropriate reliability upon reviewing the toshiba semiconductor reliability handbook (handling precautions/derating concept and me thods) and individual reliability data (i.e. reliability test report and estimated failure rate, etc). operating conditions ( t a = 25c) characteristic s symbol min typ. max unit supply voltage v cc 6 7 1 0 v ceramic oscillation frequency x in 2 4 8 mhz ambient temperature t a ( c) p d C t a power dissipation p d (w) 0 0 (1) when mounted on pcb universa l 50 mm 50 mm 1.6 mm cu 30% (2) ic only r th (j - a) = 200 c/w 1.5 1.0 0.5 50 100 150 200 (2) (1)
tb6551fg/fag 2012 - 09- 28 8 electrical characteristics ( t a = 25c, v cc = 7 v) characteristics symbol test circuit test condition min typ. max unit supply current i cc D v refout = open D 3 6 ma input current i in (1) D v in = 5 v v e , la D 20 40 a i in (2) - 1 v in = 0 v hu, hv, hw ? 40 ? 20 D i in (2) - 2 v in = 0 v cw/ccw, os, t d ? 80 ? 40 D i in (2) - 3 v in = 5 v res D 40 80 input voltage v in high D hu, hv, hw, cw/ccw, r es, os, t d v refout ? 1 D v refout v low D D 0.8 input hysteresis voltage v h D hu, hv, hw, cw/ccw, res D 0.3 D v output voltage v out (h) - 1 D i out = 2 ma u, v, w, x, y, z v refout ? 0.78 v refout ? 0.4 D v v out (l) - 1 i out = ? 2 ma u, v, w, x, y, z D 0.4 0.78 v rev (h) i out = 1 ma rev v refout ? 1.0 v refout ? 0.5 D v rev (l) i out = ? 1 ma rev D 0.5 1.0 v fg(h) i out = 1 ma fg v refout ? 1.0 v refout ? 0.5 D v fg(l) i out = ? 1 ma fg D 0.5 1.0 v refout i out = 30 ma v refout 4.5 5.0 5.5 outpu t leakage current i l (h) D v out = 0 v u, v, w, x, y, z D 0 10 a i l (l) v out = 3.5 v u, v, w, x, y, z D 0 10 output off - time by upper/lower transistor (note 6) t off(h) D t d = high or open, x in = 4.19 mhz, i out = 2 ma, os = high/low 2.2 2.6 D s t off(l) D t d = low, x in = 4.19 mhz, i out = 2 ma, os = high/low 3.0 3.8 D over - current detection v dc D i dc 0.46 0.5 0.54 v lead angle correction t la (0) D l a = 0 v or open, hall in = 100 hz D 0 D t la (2.5) D l a = 2.5 v, hall in = 100 hz 27.5 32 34.5 t la (5) D l a = 5 v, hall in = 100 hz 53.5 59 62.5 v cc monitor v cc (h) D output start operation point 4.2 4.5 4.8 v v cc (l) D no output operation point 3.7 4.0 4.3 v h D input hysteresis width D 0.5 D note 6 : t off os = high os = low 0.78 v 0.78 v t off t off 0. 78 v 0.78 v turn - on signal (u, v, w) turn - on signal ( x , y , z ) v refout ? 0.78 v t off turn - on signal (u, v, w) turn - on signal ( x , y , z ) t off v refout ? 0.78 v v refout ? 0.78 v v refout ? 0.78 v
tb6551fg/fag 2012 - 09- 28 9 functional description basic operation on start - up, the motor is driven by the square - wave turn - on signal based on a positional signal. when the positional signal reaches number of rotations f = 5 hz or higher, the rotor position is inferred from the po sitional signal and a modulation wave is generated. the modulation wave and the triangular wave are compared; the sine - wave pwm signal is then generated and the motor is driven. from start to 5 hz: when driven by square wave (120 turn - on) f = f osc /(2 12 32 6) 5 hz or higher : when driven by sine - wave pwm (180 turn - on) when f osc = 4 mhz, approx. 5 hz function to stabilize bootstrap voltage (1) w hen voltage instruction is input at v e 0.2 v: the lower transistor is turned on at the regular (carrier) cycle. (on duty is approx. 8%.) (2) when voltage instruction is input at v e > 0.2 v: during sine - wave drive, the drive signal is output as it is. during square - wave drive, the lower transistor is forcibly turned on at the regular (carrier) cycle. (on duty is approx. 8%.) note: at startup, to charge the upper transistor gate power supply, turn the lower transistor on for a fixed time with v e 0.2 v. dead time function: upper/lower transistor output off - time when the motor is driven by a sine - wave pwm, dead time is generated digitally in the ic to prevent a ny short circuit caused by the simultaneous turning on of upper and lower external powe r devices . when a square wave is generated in full duty cycle mode, the dead time function is turned on to prevent a short circuit. t d pin internal counter t off high or open 11/f osc 2.6 s low 16/f osc 3.8 s t off values above are obtained when f os c = 4.19 mhz. f osc = reference clock ( ceramic oscillation) correcting l ead angle the lead angle can be corrected in the turn - on signal range from 0 to 58 in relation to the induced voltage. analog input from la pin (0 v to 5 v divided by 32): 0 v = 0 5 v = 58 (when more than 5 v is input, 58 ) s etting c arrier frequency this feature sets the triangular wave cycle (carrier cycle) necessary for generating the pwm signal. (the triangular wave is used for forcibly turning on the lower transistor when the mo tor is driven by square wave.) carrier cycle = f osc / 252 (hz) f osc = reference clock ( ceramic oscillation) s witching the output of turn - on signal this function switches the output of the turn - on signal between high and low. pin os: high = active high low = active low
tb6551fg/fag 2012 - 09- 28 10 outputting r everse rotation detection signal the direction of motor rotation is detected for every electrical angle of 360 . ( the output is h igh immediately after reset . ) the rev terminal increases to a 18 0 turn - on mode at the time of low ( hall in 5 hz). cw/ccw pin actual motor rotating direction rev pin low (cw) cw ( forward ) low ccw ( reverse ) high high (ccw) cw ( forward ) high ccw ( reverse ) low protecting input pin 1. over - current protection (pin i dc ) when the dc - link - current exceeds the internal reference voltage, gate block protection is performed. over - current protection is released for each carrier frequency. reference voltage = 0.5 v (typ.) 2. gate block protection (pin res) when the input signal level is low, the output is turned o ff; when the signal is high, the output is restarted. abnormalities are detected externally, and the signal is input to the pin res. res pin os pin output turn - on signal (u, v, w, x, y, z) low low high high low (when res = low, bootstrap capacitor ch arging stops.) 3. internal protection ? positional signal abnormality protection when the positional signal is hhh or lll, the output is turned off ; otherwise, the output is restarted . ? low power supply voltage protection (v cc monitor) o utside the operating volt age range , the turn - on signal output is kept at high impedance to prevent damage caused by short - circuiting of power components when the power supply is turned on or off . output at high impedance turn - on signal power s upply voltage 4.5 v (typ. ) 4.0 v (typ. ) gnd v m v cc output at high impedance output
tb6551fg/fag 2012 - 09- 28 11 operation flow note: output on time is decreased by the dead time (carrier fr equency 92% ? t d 2). sine - wave pattern ( modulat ion signal ) triangular wave ( carrier frequency ) position detector counter system clock generator phase matching positional signal (hall ic) voltage instruction oscillator comparator phase w phase v phase u u x v y w z voltage instruction v e driven by sine wave modulation ratio (modulation signal) 0.2 v (typ.) 100% 5 v (v refout ) 0 voltage instruction v e driven by square wave output on duty (u, v, w) 0.2 v (typ.) 92% ( note ) 4.6 v
tb6551fg/fag 2012 - 09- 28 12 the modulation waveform is generated using hall signals. t he modulation waveform is then compared with the triangular wave and a sine - wave pwm signal is generated. the time (electrical angle : 60) from the rising (or falling) ed ges of the three hall signals to the next falling (or rising) edges is counted. the counted time is used as the data for the next 60 phase of the modulation waveform. there are 32 items of data for the 60 phase of the modulation waveform. the time width of one data item is 1/32 of the time width of the 60 phase of the previous modulation waveform. the modulation waveform moves forward by th is width. in the above diagram, the modulation waveform (1) ' data moves forward by the 1/32 time width of the time (1) from hu: to hw:. similarly, data (2) ' moves forward by the 1/32 time width of the time (2) from hw: to hv : . if the next edge does not occur after the 32 data items end, the next 32 data items move forward by the same time width until the next ed ge occurs. the modulation wave is brought into phase with every edge of the hall signal. the modulation wave is reset in synchronization with the rising and falling edges of the hall signal at every electrical angle of 60. thus, when the hall device is not placed in the correct position or during acceleratin g or deceleratin g , the modulation waveform is no t cont inuous at every reset. * t s v (1) 1 2 3 4 5 6 30 31 32 32 data items * t * t = t (1) 1/32 hu hv hw s u s v sw (5) (2) (6) (1) (3) (6) (1) (2) (3) * hu, hv, hw: hall signals
tb6551fg/fag 2012 - 09- 28 13 timing charts hall signal (input) hu hv hw fg signal (output) fg turn - o n signal when driven by square wave (output) u v w x y z s u s v s w modulation waveform when driven by sine wave (inside of ic) forward hu hv hw fg signal (output) fg u w x y z s u s v s w hall signal (input) v reverse turn - on signal when driven by square wave (output) modulation waveform when driven by sine wave (inside of ic)
tb6551fg/fag 2012 - 09- 28 14 operating waveform when driven by square wave (cw/ccw = low, os = high) to stabilize the bootstrap voltage, the lower outputs (x, y, and z) are always turned on at the carrier cycle even during off time. at that time, the upper outputs (u, v, and w) are assigned dead time and turned off at the timing when the lower outpu ts are turned on. (t d varies with input v e. ) carrier cycle = f osc /252 (hz) dead time: t d = 16/f osc (s) (when v e = 4.6 v or more) t onl = carrier cycle 8% (s) (uniform regardless of ve input) when the motor is driven by a square wave, acceleration or dece leration is determined by voltage v e . the motor accelerates or decelerates according to the on duty of t onu. (s ee the diagram for output on duty on page 11 . ) note: the motor is driven by a square wave if rev = high, i.e., if the hall signals at start -up are 5 hz (f osc = 4 mhz) or lower and the motor is rotating in the reverse direction to that of the tb6551 fg/fag setting. hall signal h u h v h w enlarged waveform u x v y w z output waveform t onu t onl t d w z t d
tb6551fg/fag 2012 - 09- 28 15 operating waveform when driven by sine - wave pwm (cw/ccw = low, os = high) when the motor is driven by a sine wave, the motor is accelerated or decelerated according to the on duty of t onu when the amplitude of the modulation symbol changes by voltage v e (see the diagram of output on duty on page 11): triangular wave frequency = carrier frequency = f osc /252 (hz). note: the motor is driven by a sine wave if rev = low, i.e., if the hall signals at start - up are 5 hz (f osc = 4 mhz) or higher and the motor is rotating in the same direction as that of the tb6551 fg/fag setting. generation inside of ic phase phase phase modulation signal triangular wave (carrier frequency) v uv ( u - v ) v vw ( v - w ) v wu ( w - u ) inter - line voltage output waveform u x v y w z
tb6551fg/fag 2012 - 09- 28 16 example of ap plication circuit note 7 : connect as required to the ground to prevent ic malfunction due to noise. note 8 : connect p- gnd to signal ground on the application circuit. note 9 : utmost care is necessary in the design of the output, v cc , vm , and gnd lines since the ic may be destroyed by short - circuiting between outputs, air contamination faults, or faults due to improper grounding, or by short - circuiting between contiguous pins. v refout system clock generator position detector counter 5 - bit ad triangular wave generator 6 - bit output waveform generator select ing d ata s witching 120/180 & gate block protection on/off s etting d ead time charger 120 - turn - on matrix power - on reset protection & reset 12 phase matching 4 bit fg rotati ng direction st / sp cw / ccw err gb comparator comparator comparator comparator pwm hu hv hw 120 /180 phase w phase u os phase v brk (chg) mcu hall ic signal ( note 7 ) ( note 7 ) ( note 8 ) 6 v to 10 v x in x ou t hu h v hw v e v cc p - gnd s - gnd v ref res i dc cw / ccw fg rev 14 15 21 20 19 22 2 13 24 11 3 18 17 16 23 la 4 7 5 8 6 9 10 t d u x v y w z 1 regulator m power device
tb6551fg/fag 2012 - 09- 28 17 package dimensions weight: 0.33 g (t yp.)
tb6551fg/fag 2012 - 09- 28 18 package dimensions weight : 0.28 g ( typ. ) p - ssop24 - 0613 - 1.00 - 001
tb6551fg/fag 2012 - 09- 28 19 notes on contents 1. block diagrams some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. equivalent circuits the equival ent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. timing charts timing charts may be simplified for explanatory purposes. 4. application circuits the application circuits shown in this document are p rovided for reference purposes only. thorough evaluation is required, especially at the mass production design stage. toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. test circui ts components in the test circuits are used only to obtain and confirm the device characteristics. these components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. ic usage considerations note s on handling of ics [1 ] the absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. do not exceed any of these ratings. exceeding the rating(s) may cause the device breakdown, damage or deteri oration, and may result injury by explosion or combustion. [2 ] do not insert devices in the wrong orientation or incorrectly. make sure that the positive and negative terminals of power supplies are connected properly. otherwise, the current or power cons umption may exceed the absolute maximum rating, and exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. in addition, do not use any device that is applied the current with inser ting in the wrong orientation or incorrectly even just one time.
tb6551fg/fag 2012 - 09- 28 20 points to remember on handling of ics (1) over current protection circuit over current protection circuits (referred to as current limiter circuits) do not necessarily protect ics under al l circumstances. if the o ver current protection circuits operate against the over current, clear the over current status immediately. depending on the method of use and usage conditions, such as exceeding absolute maximum ratings can cause the over curren t protection circuit to not operate properly or ic breakdown before operation. in addition, depending on the method of use and usage conditions, if over current continues to flow for a long time after operation, the ic may generate heat resulting in breakd own. (2 ) back - emf when a motor rotates in the reverse direction, stops or slows down abruptly , a current flow back to the motor s power supply due to the effect of back - emf. if the current sink capability of the power supply is small, the device s motor power supply and output pins might be exposed to conditions beyond a bsolute maximum ratings. to avoid this problem, take the effect of back - emf into consideration in system design
tb6551fg/fag 2012 - 09- 28 21 restrictions on product use ? toshiba corporation, and its subsidiaries and affiliates (collectively "toshiba"), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively "product") without notice. ? this document and any information herein may not be reproduced without prior written permission from toshiba. even with toshiba's written permission, reproduction is permissible only if reproduction is without alteration/omission. ? though toshiba works continually to improve product's quality and reliability, produc t can malfunction or fail. customers are responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, softwar e and systems which minimize risk and avoid situations in which a malfunction or failure o f product could cause loss of human life, bodily injury or damage to property, including data loss or corruption. before customers use the product, create designs including t he product, or incorporate the product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant toshiba information, including without limitation, this document, the specifications, the data sheets and applic ation notes for product and the precautions and conditions set forth in t he "toshiba semiconductor reliability handbook" and (b) the instructions for the application with which the product will be used with or for. customers are solely responsible for all as pects of their own product design or applications, including but not li mited to (a) determining the appropriateness of the use of this product in such design or applications; (b) evaluating and determining the applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample app lication circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications. toshiba assumes no liability for customers' product design or applications. ? product is neither intended nor warranted for use in equipments or systems that require extraordinarily high levels of quality and/or reliability, and/or a malfunction or failure of which may cause loss of human life, bodily injury, serious property damage and/or serious public impact ( " unintended us e " ). except for specific applications as expressly stated in this document, unintended use includes, without limitation, equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment, equipment used for automobiles, trai ns, ships and other transportation, traffic signaling equipment, equipment used to control combustions or explosions, safety devices, elevators and escalators, devices related to electric power, and equipment used in finance - related fields. if you use prod uct for unintended use, toshiba assumes no liability for product. for details, please contact your toshiba sales representative. ? do not disassemble, analyze, reverse - engineer, alter, modify, translate or copy product, whether in whole or in part. ? produ ct shall not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable laws or regulations. ? the information contained herein is presented only as guidance for product use. no responsibilit y is assumed by toshiba for any infringement of patents or any other intellectual property rights of third parties that may result from the use of product. n o license to any intellectual property right is granted by this document, whether express or implie d, by estoppel or otherwise. ? absent a written signed agreement, except as provided in the relevant terms and conditions of sale for product, and to the maximum extent allowable by law, toshiba (1) assumes no liability whatsoever, including without limitation, indirect, consequential, special, or incidental damages or loss, incl uding without limitation, loss of profits, loss of opportunities, business interruption and loss of data, and (2) disclaims any and all express or implied warranties and conditions related to sale, use of product, or information, including warranties or co nditions of merchantability, fitness for a particular purpose, accuracy of information, or noninfringement. ? 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